Industry Experience

Dukosi · Jun 2026 — Aug 2026

ASIC Digital Team Intern

• Completed professional Cadence System Verilog Design & Verification training, applying the skills to RTL (Register Transfer Level) development, simulation and testbench creation.
• Performed RTL power analysis using Cadence Joules across multiple DSP (Digital Signal Processing) test cases to identify power consumption trends and optimisation opportunities.
• Investigated clock-gating techniques using Joules proto-synthesis and compared their impact against the original RTL implementation.
• Analysed an existing DSP architecture, including its RTL behaviour, ARM APB (Advanced Peripheral Bus) interface, simulation flow and switching activity.
• Created a simulation test case in System Verilog and simulated it using Cadence Xcelium and SimVision, using waveform analysis to validate and understand the design behaviour.
• Designed and implemented a 2-way set-associative cache in System Verilog with LRU replacement, write-through operation, ARM APB interfacing, hit/miss detection and error handling.
• Developed an ARM APB memory model and System Verilog testbench to verify cache reads, writes, hit/miss behaviour and APB error conditions.
• Worked extensively in Linux-based engineering environments, using tools such as Confluence, Jira and remote development platforms.
• Produced clear technical documentation and engineering reports covering implementation details, verification methods, experiments and results.
• Presented technical work and findings to the ASIC Digital team, strengthening my ability to communicate engineering concepts clearly and professionally.